? semiconductor components industries, llc, 2009 september, 2009 ? rev. 3 1 publication order number: nb7v52m/d nb7v52m 1.8v / 2.5v differential d flip-flop w/ reset and cml outputs multi ? level inputs w/ internal termination description the nb7v52m is a 10 ghz differential d flip ? flop with a differential asynchronous reset. the differential d/d , clk/clk and r/r inputs incorporate dual internal 50 termination resistors and will accept lvpecl, cml, lvds logic levels. when clock transitions from logic low to high, data will be transferred to the differential cml outputs. the differential clock inputs allow the nb7v52m to also be used as a negative edge triggered device. the 16 ma differential cml outputs provide matching internal 50 termination and produce 400 mv output swings when externally receiver terminated with a 50 resistor to v cc . the nb7v52m is offered in a low profile 3 mm x 3 mm 16 ? pin qfn package. the nb7v52m is a member of the gigacomm ? family of high performance clock products. application notes, models, and support documentation are available at www.onsemi.com. features ? maximum input clock frequency > 10 ghz ? maximum input data rate > 10 gb/s ? random clock jitter < 0.8 ps rms, max ? 200 ps typical propagation delay ? 35 ps typical rise and fall times ? differential cml outputs, 400 mv peak ? to ? peak, typical ? operating range: v cc = 1.71 v to 2.625 v with v ee = 0 v ? internal 50 input termination resistors ? qfn ? 16 package, 3mm x 3mm ? ? 40 c to +85 c ambient operating temperature ? these are pb ? free devices a = assembly location l = wafer lot y = year w = work week = pb ? free package (note: microdot may be in either location) *for additional marking information, refer to application note and8002/d. marking diagram* qfn ? 16 mn suffix case 485g http://onsemi.com see detailed ordering and shipping information in the package dimensions sect ion on page 9 of this data sheet. ordering information 1 nb7v 52m alyw 16 1 figure 1. logic diagram q q reset d flip ? flop clk vtclk d vtd r d vtd clk vtclk r vtr vtr
nb7v52m http://onsemi.com 2 vtclk clk clk vtclk vtr r r vtr vcc q q vee vtd d d vtd 5678 16 15 14 13 12 11 10 9 1 2 3 4 nb7v52m exposed pad (ep) figure 2. pin configuration (top view) table 1. input/output select truth table r d clk q h x x l l l z l l h z h z = low to high transition x = don?t care table 1. pin description pin name i/o description 1 vtd ? internal 50 termination pin for d 2 d lvpecl, cml, lvds input noninverted differential data input. (note 1) 3 d lvpecl, cml, lvds input inverted differential data input. (note 1) 4 vtd ? internal 50 termination pin for d 5 vtclk ? internal 50 termination pin for clk 6 clk lvpecl, cml, lvds input noninverted differential clock input. (note 1) 7 clk lvpecl, cml, lvds input inverted differential clock input. (note 1) 8 v tclk ? internal 50 termination pin for clk 9 vee ? negative supply voltage. (note 2) 10 q cml output inverted differential output 11 q cml output noninverted differential output 12 vcc ? positive supply voltage. (note 2) 13 vtr ? internal 50 termination pin for r 14 r lvpecl, cml, lvds input noninverted asynchronous differential reset input. (note 1) 15 r lvpecl, cml, lvds input inverted asynchronous differential reset input. (note 1) 16 vtr ? internal 50 termination pin for r ? ep ? the exposed pad (ep) on the qfn ? 16 package bottom is thermally connected to the die for improved heat transfer out of package. the exposed pad must be attached to a heat ? sinking conduit. the pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to vee on the pc board. 1. in the dif ferential configuration when the input termination pins (vtx, vtx ) are connected to a common termination voltage or left open, and if no signal is applied on clk/clk input, then the device will be susceptible to self ? oscillation. 2. all vcc and gnd pins must be externally connected to a power supply for proper operation.
nb7v52m http://onsemi.com 3 table 2. attributes characteristics value esd protection human body model machine model > 2 kv > 200 v moisture sensitivity 16 ? qfn level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 173 meets or exceeds jedec spec eia/jesd78 ic latchup test for additional information, see application note and8003/d. table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply v ee = 0 v 3.0 v v io positive input/output voltage v ee = 0 v ? 0.5 vio vcc + 0.5 ? 0.5 to v cc +0.5 v v inpp differential input voltage |clk ? clk |, |d ? d |, |r ? r | 1.89 v i out output current through r tout (50 resistor) continuous surge 34 40 ma i in input current through r tin (50 resistor) 40 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 3) 0 lfpm 500 lfpm qfn ? 16 qfn ? 16 42 35 c/w c/w jc thermal resistance (junction ? to ? case) (note 3) qfn ? 16 4 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 3. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
nb7v52m http://onsemi.com 4 table 4. dc characteristics, multi ? level inputs v cc = 1.71 v to 2.625 v, v ee = 0 v, t a = ? 40 c to +85 c (note 4) symbol characteristic min typ max unit power supply current i cc power supply current (inputs and outputs open) v cc = 2.5 v v cc = 1.8 v 90 70 110 90 ma cml outputs v oh output high voltage (note 5) v cc = 2.5 v v cc = 1.8 v v cc ? 30 2470 1770 v cc ? 10 2490 1790 v cc 2500 1800 mv v ol output low voltage (note 5) v cc = 2.5 v v cc ? 650 1850 v cc ? 500 2000 v cc ? 400 2100 mv v cc = 1.8 v v cc ? 600 1200 v cc ? 450 1350 v cc ? 350 1450 differential clock inputs driven single ? ended (note 6) (figures 5 and 7) v th input threshold reference voltage range (note 7) 1000 v cc ? 100 mv v ih single ? ended input high voltage v th + 100 v cc mv v il single ? ended input low voltage v ee v th ? 100 mv v ise single ? ended input voltage (v ih ? v il ) 200 1200 mv differential d/d , clk/clk , r/r inputs driven differentially (figures 6 and 8) (note 8) v ihd differential input high voltage 1100 v cc mv v ild differential input low voltage v ee v cc ? 100 mv v id differential input voltage (v ihd ? v ild ) 100 1200 mv v cmr input common mode range (differential configuration, note 9) (figure 10) 1050 v cc ? 50 mv i ih input high current (vt x /vt x open) ? 250 250 a i il input low current (vt x /vt x open) ? 250 250 a termination resistors r tin internal input termination resistor 45 50 55 r tout internal output termination resistor 45 50 55 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. input and output parameters vary 1:1 with v cc . 5. cml outputs loaded with 50 to v cc for proper operation. 6. v th , v ih , v il,, and v ise parameters must be complied with simultaneously. 7. v th is applied to the complementary input when operating in single ? ended mode. 8. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously. 9. v cmr min varies 1:1 with v ee , v cmr max varies 1:1 with v cc . the v cmr range is referenced to the most positive side of the dif ferential input signal.
nb7v52m http://onsemi.com 5 table 5. ac characteristics v cc = 1.71 v to 2.625 v; v ee = 0 v; t a = ? 40 c to 85 c (note 10) symbol characteristic min typ max unit f max maximum input clock frequency 10 12 ghz f data max maximum input data rate (prbs23) 10 12 gbps v outpp output voltage amplitude (@ v inppmin ) fin 7 ghz (see figures 3 and 10, note 11) fin 10 ghz 300 250 400 400 mv t plh , t phl propagation delay to differential outputs, @ 1 ghz, measured at differential cross ? point clk/clk to q/q r/r to q/q 200 300 350 600 ps t s setup time (d to clk) 40 15 ps t h hold time (d to clk) 50 20 ps t rr reset recovery 275 200 ps t pw minimum pulse width r/r 1 ns t jitter rj ? output random jitter (note 12) f in 10 ghz 0.2 0.8 ps rms v inpp input voltage swing (differential configuration) (note 13) 100 1200 mv t r, , t f output rise/fall times @ 1 ghz (20% ? 80%), q, q 20 35 50 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. measured using a 400 mv v inpp source, 50% duty cycle clock source. all output loading with external 50 to v cc . input edge rates 40 ps (20% ? 80%). 11. output voltage swing is a single ? ended measurement operating in differential mode. 12. additive rms jitter with 50% duty cycle clock signal. 13. input voltage swing is a single ? ended measurement operating in differential mode. figure 3. clock output voltage amplitude (v outpp ) vs. input frequency (f in ) at ambient temperature (typ) fin, clock input frequency (ghz) output voltage amplitude (mv) 500 450 400 350 300 200 012 3456 78 q/q output figure 4. simplified input structure 250 50 50 d v cc vtd vtd d r c r c i 9101112 r tin r tin
nb7v52m http://onsemi.com 6 clk v th clk v th figure 5. differential input driven single ? ended v ih v il v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v thmax v thmin v ee v th clk/d/r clk /d /r v ildmax v ihdmax v ihdtyp v ildtyp v ihdmin v ildmin v cmr v ee v id = v ihd ? v ild v cc clk clk q q t plh t phl v outpp = v oh (q) ? v ol (q) v inpp = v ih (clk) ? v il (clk) v ihd v ild v id = |v ihd(clk) ? v ild(clk)| clk clk figure 6. differential inputs driven differentially figure 7. v th diagram figure 8. differential inputs driven differentially figure 9. v cmr diagram figure 10. ac reference measurement clk clk v cmrmax v cmrmin clk
nb7v52m http://onsemi.com 7 figure 11. typical cml output structure and termination v cc 50 r tout 50 r tout 16 ma 50 50 v cc nb7v52m receiver q q v ee driver device receiver device qd figure 12. typical termination for cml output driver and device evaluation q d v cc 50 50 z = 50 z = 50 dut
nb7v52m http://onsemi.com 8 lvpecl driver v cc gnd/v ee z o = 50 v th = v cc ? 2 v z o = 50 nb7v52m d 50 50 d v ee figure 13. lvpecl interface lvds driver v cc gnd z o = 50 z o = 50 nb7v52m 50 50 v ee figure 14. lvds interface v cc v cc figure 15. standard 50 load cml interface figure 16. capacitor ? coupled differential interface (v t /v t connected to external v refac ; v refac bypassed to ground with 0.1 f capacitor) figure 17. capacitor ? coupled single ? ended interface (v t /v t connected to external v refac ; v refac bypassed to ground with 0.1 f capacitor) v td v td d d v td v td cml driver v cc gnd z o = 50 v t = v t = v cc z o = 50 nb7v52m 50 50 v ee v cc d d v td v td v cc differential driver v cc gnd/v ee z o = 50 v th = external v refac z o = 50 nb7v52m 50 50 v ee v cc d d v td v td v th v td v td v th single ? ended driver v cc gnd/v ee z o = 50 v th = external v refac nb7v52m 50 50 v ee v cc d d v th
nb7v52m http://onsemi.com 9 ordering information device package shipping ? nb7v52mmng qfn ? 16 (pb ? free) 123 units / rail NB7V52MMNHTBG qfn ? 16 (pb ? free) 100 / tape & reel nb7v52mmntxg qfn ? 16 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
nb7v52m http://onsemi.com 10 package dimensions 16 pin qfn case 485g ? 01 issue d 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag ??? ??? ??? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k l 0.30 0.50 exposed pad 0.18 typ l1 detail a l alternate terminal constructions ?? ?? 0.00 0.15 mm inches scale 10:1 0.50 0.02 0.575 0.022 1.50 0.059 3.25 0.128 0.30 0.012 3.25 0.128 0.30 0.012 exposed pad *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 nb7v52m/d the products described herein (nb7v52m), may be covered by u.s. patents including 6,362,644 . there may be other patents pending. gigacomm is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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